1. Field of the Invention
The present invention relates to the control of spindle speed in a disk drive system. More particularly, the present invention relates to control of the speed of revolution of a disk in a disk drive system.
2. Art Background
The spindle control controls the speed of rotation of the disk in a disk drive. Optimally, it is desirable to maintain the speed of rotation at a constant rate to minimize data errors and accurately track head movement on the disk. As the speed measurement itself is not easily measured, time between events are measured in order to derive a relative speed parameter. For example, time between pulses, hard sector marks and back EMF zero crossings are referenced.
A block diagram illustration of a spindle control is shown in FIG. 1. FIG. 1 is a current drive based system. A similar block diagram is readily apparent for a voltage drive based system. Referring to FIG. 1, clock reference 10 is input to error detector 70 which generates an error signal. The error signal is input to compensator 20 which generates the motor current as output 30 to drive the motor 40 which drives the speed of rotation of the disk drive at a velocity .omega. 50. The motor speed is converted by converter 60 from a frequency value to a time parameter and is utilized as input to error detector 70. Thus, if the velocity is too high, the error signal will be negative causing compensator 20 to output less motor current and consequently slowing down the motor, and if the velocity is too low, the error signal will be positive causing compensator 20 to output more motor current, thereby speeding up the motor. The compensator serves two purposes. First it puts an integrator in the system which allows the system to have zero steady-state speed error. Secondly, it adds a zero, pole and gain term to the system to allow for stabilization and optimization. The transfer function of the compensator is given by the equation: ##EQU1## where Kc is a generic gain term, 1/s is the integrator, (s+z) is the zero, and (s+p) is the pole. As is known in the art, proper choice of all these terms will allow the designer of the system to adjust the crossover frequency and phase margin for stability as well as tailor the dynamics of the loop to suit the requirements of the application.
The clock reference 10 is a value indicative of the spin speed, particularly a number representing the number of clock ticks between certain events. The error generator 70 compares the actual count to the clock reference 10 and produces an error signal which is proportional to the magnitude of spin speed error which is input to compensator 20 to drive the motor 40.
Because time is measured in terms of events, the system can be configured to be sampled as shown in FIG. 2. The compensator 90 and error generator 85 are accomplished digitally inside a microprocessor. The compensator 90 and error generator 85, preferably implemented by a microprocessor, generate a digital output which is converted to an analog signal via the zero-order hold circuit 95. The output of the zero-order hold circuit 95 is subsequently input to motor 100 to generate the rotation at frequency .omega. 105. The motor 100 output is further input to the frequency to time conversion circuit 115 which translates the frequency value to a time value that is sampled by switch 117 at specified time intervals. The measured time is obtained via a digital counter (not shown) which counts clock ticks between events or known positions on the disk. Even though the sampling is spatial in nature, when spinning at high speeds, the sampling can be thought of as occurring at a constant rate.
A problem exists with the system as the counter used to perform the time measurement requires a fast clock in order that there is sufficiently high resolution to accurately set the spin speed. For example, if the time is counted between sectors and there were only a hundred counts available, then the spin speed would be quantized to about 1%. One way to solve the problem is to increase the clock speed and therefore measure more counts per event. However, the clock speed is determined by other system considerations, typically the clock speed of the microprocessor utilized in the system. Thus, the designer may not have the freedom to change the system clock speed. Another option is to sample over a longer period of time, for instance two or more hard sectors. This causes the sample rate of the system to be lowered, which is generally an undesirable trade off. Furthermore, the gain of the loop and clock speed are proportional. Thus, if the clock speed is increased, the gain somewhere else in the loop must be decreased to compensate. The compensator is the most ready place to change the overall gain of the system. Lowering this gain can cause output quantization problems, therefore, for example, to cause a single bit of compensator output, a large change in speed would need to occur.